1. Field of the Invention
The present invention relates generally to an integrated circuit ("IC"). The invention relates more specifically to an IC having, and a process for providing, an oxide layer of plural thicknesses on a substrate.
2a. Cross Reference to Related Applications
The following copending U.S. patent application is assigned to the assignee of the present application, is related to the present application and its disclosure is incorporated herein by reference:
(A) Ser. No. 08/561,306 Attorney Docket No. AMDI8125MCF/GGG/PHH! by Barsan, et al and entitled MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE.
2b. Cross Reference to Related Patents
The following U.S. patent is assigned to the assignee of the present application, is related to the present application and its disclosure is incorporated herein by reference:
(A) U.S. Pat. No. 4,924,278 issued May 8, 1990, to Logie and entitled EEPROM USING A MERGED SOURCE AND CONTROL GATE.
3. Description of the Related Art
IC devices, such as Electrically Erasable and Reprogrammable Read-Only Memory ("EEPROM") devices and Programmable Logic Devices ("PLD"s), commonly contain transistors and other circuit elements that operate at different voltage levels or switching speeds. A single IC device may include plural transistors respectively operating at high and low voltages. A non-volatile memory cell such as disclosed in U.S. Pat. No. 4,924,278 referenced above, for example, may include a first transistor that operates at a relatively high drain-to-source voltage level, for example 12 volts, for program and erase operations as well as a second transistor that operates at a relatively low drain-to-source voltage level, for example 3.3 volts, for read operations. High voltage transistors are usually integrally formed with a relatively thick gate oxide layer ("GOX"). The relatively thick gate oxide helps to prevent transistor breakdown in a high voltage operating environment. However, it is preferable that a read transistor is formed with relatively thin gate oxide. Thin gate oxide helps to increase the switching speed of the transistor by increasing saturation current I.sub.dsat in short channel length designs. Transistor elements having relatively short gate lengths and thin oxide layers generally provide increases in operating speeds.
As process technologies evolve toward shorter gate lengths, it is desirable to reduce the thickness of a gate oxide layer in logic transistors even further in order to achieve greater operating speed. However, some circuit elements contained on an IC device may not be scalable in this manner.
For example, the memory cell described in U.S. Pat. No. 4,924,278 referenced above, commonly comprises a tunnel capacitor that includes a tunnel oxide ("TOX") layer. To have an operative tunneling effect, the TOX should be in a certain range of thicknesses. This is dictated by electron physics. As such, tunnel oxide thickness cannot be scaled down in the same manner as a low voltage GOX. This tunnel capacitor may suffer from significant endurance and data retention problems if the tunnel oxide layer is made too thin. Tunneling may be substantially impaired if it is made too thick.
It may be desirable to have a non-volatile memory cell formed with at least three different thicknesses of gate oxide ("GOX"). Write transistors should have a relatively large first thickness of gate oxide ("HVGOX") to accommodate high voltage program and erase operations. Read transistors should have relatively smaller, second thickness of gate oxide ("LVGOX") to yield faster switching speed at lower voltages. Tunnel capacitors may call for an independently set, third thickness of gate oxide ("TOX").
One method of forming differing oxide layer thicknesses on the same substrate involves the following multiple mask and oxide formation steps: (1) A first oxide sublayer is initially grown on a wafer substrate. (2) Thereafter, parts of the first oxide sublayer are usually masked with a photoresist mask layer and remaining unmasked oxide is stripped or etched away from the wafer substrate. (3) Thereafter, the photoresist mask layer is typically stripped away. (4) A second oxide sublayer is grown, adding to the thickness of the first oxide sublayer. Thicker oxide is produced where the first oxide sublayer resided and thinner oxide is produced where the first oxide had been earlier removed.
Unfortunately, the photoresist mask layer used to mask the first oxide sublayer usually leaves residue on the surface of the first oxide sublayer after removal. Photoresist residue on the first oxide sublayer typically reduces the overall quality of the subsequent thicker oxide that is thermally grown thereafter. Moreover, this method requires the performance of multiple photoresist mask layer and oxide layer formation steps in a manufacturing process. These extra steps typically increase the overall costs of a manufacturing process and degrade reliability as well as yield.
In another method: (1) A first oxide layer is initially grown on a wafer surface. (2) Next, a portion of the first oxide layer is masked with a photoresist mask layer. (3) The remaining unmasked oxide is then etched back to form a thinner oxide layer. Unfortunately, the last etching step to form the thinner oxide is usually difficult to control and hinders the precision with which oxide layers are formed.
Various patents and articles have described the use of nitrogen in forming oxide layers. U.S. Pat. No. 5,308,787, Hong, et al., entitled "Uniform Field Oxidation for Locos Isolation", dated May 3, 1994 ("Hong"), describes the use of nitrogen in hindering oxide formation to form a two-thickness layer.
Likewise, "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing" by Brian Doyle, Member, IEEE, Hamid R. Soleimani and Ara Philipossian, as published in IEEE Electron Device Letters, Vol. 16, No. 7, July 1995 ("Doyle"), describes using nitrogen to retard or reduce oxide growth in forming various oxide layers.
It is desirable to provide an integrated circuit device, such as a non-volatile memory cell, having at least three different, precisely controlled thicknesses of GOX.
Further, it is desirable to provide a process for manufacturing the above circuit in a reliable and cost-effective manner without multiple mask and oxidation formation process steps.